Low-damage processing and polishing processes and evaluation of SiC and GaN wafer substrates.
Latest polishing technology for various GaN/SiC related materials with high hardness and brittleness.
★What does the future hold for technologies that support large-diameter processing and mass production techniques? ★We will also introduce the characteristics of the residual processing altered layer remaining during SiC wafer processing, its impact on subsequent processes, and analysis techniques for the altered layer. ★We are currently conducting a pre-content request service! We welcome your practical challenges! 【Venue】 Tekno Kawasaki, 5th Floor, 5th Training Room【Kanagawa, Kawasaki】 【Date and Time】 September 17, 2013 (Tuesday) 11:00-15:45 【Instructors】 Part 1: Dr. Tomohisa Kato, Team Leader and Senior Researcher, Advanced Power Electronics Research Center, National Institute of Advanced Industrial Science and Technology (AIST) Here is the homepage of the Advanced Power Electronics Research Center. Part 2: Representative from Namiki Precision Jewel Co., Ltd., NJC Technology Research Institute Part 3: Professor Kazuto Yamauchi, Graduate School of Engineering, Osaka University
- Company：AndTech
- Price：10,000 yen-100,000 yen
